diff --git a/configs/am335x_nand4k_defconfig b/configs/am335x_nand4k_defconfig
new file mode 100644
index 0000000..6aabd3e
--- /dev/null
+++ b/configs/am335x_nand4k_defconfig
@@ -0,0 +1,5 @@
+CONFIG_SPL=y
+CONFIG_SYS_EXTRA_OPTIONS="NAND,NAND_4K"
+CONFIG_CONS_INDEX=1
++S:CONFIG_ARM=y
++S:CONFIG_TARGET_AM335X_EVM=y
diff --git a/board/ti/am335x/board.c b/board/ti/am335x/board.c
index 0739e60..f2349c7 100644
--- a/board/ti/am335x/board.c
+++ b/board/ti/am335x/board.c
@@ -45,39 +45,8 @@ static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
  */
 static int read_eeprom(struct am335x_baseboard_id *header)
 {
-	/* Check if baseboard eeprom is available */
-	if (i2c_probe(CONFIG_SYS_I2C_EEPROM_ADDR)) {
-		puts("Could not probe the EEPROM; something fundamentally "
-			"wrong on the I2C bus.\n");
-		return -ENODEV;
-	}
-
-	/* read the eeprom using i2c */
-	if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 2, (uchar *)header,
-		     sizeof(struct am335x_baseboard_id))) {
-		puts("Could not read the EEPROM; something fundamentally"
-			" wrong on the I2C bus.\n");
-		return -EIO;
-	}
-
-	if (header->magic != 0xEE3355AA) {
-		/*
-		 * read the eeprom using i2c again,
-		 * but use only a 1 byte address
-		 */
-		if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 1, (uchar *)header,
-			     sizeof(struct am335x_baseboard_id))) {
-			puts("Could not read the EEPROM; something "
-				"fundamentally wrong on the I2C bus.\n");
-			return -EIO;
-		}
-
-		if (header->magic != 0xEE3355AA) {
-			printf("Incorrect magic number (0x%x) in EEPROM\n",
-					header->magic);
-			return -EINVAL;
-		}
-	}
+	char ar[] = {0xaa, 0x55, 0x33, 0xee, 'A', '3', '3', '5', 'U', 'S', 'O', 'M', 0};
+	memcpy((char *)header, (char *)&ar, sizeof(ar));
 
 	return 0;
 }
@@ -229,7 +198,7 @@ void am33xx_spl_board_init(void)
 	/* Get the frequency */
 	dpll_mpu_opp100.m = am335x_get_efuse_mpu_max_freq(cdev);
 
-	if (board_is_bone(&header) || board_is_bone_lt(&header)) {
+	if (board_is_bone(&header) || board_is_bone_lt(&header) || board_is_usomiq(&header)) {
 		/* BeagleBone PMIC Code */
 		int usb_cur_lim;
 
@@ -375,6 +344,8 @@ const struct dpll_params *get_dpll_ddr_params(void)
 		return &dpll_ddr_evm_sk;
 	else if (board_is_bone_lt(&header))
 		return &dpll_ddr_bone_black;
+	else if (board_is_usomiq(&header))
+		return &dpll_ddr_bone_black;
 	else if (board_is_evm_15_or_later(&header))
 		return &dpll_ddr_evm_sk;
 	else
@@ -459,7 +430,7 @@ void sdram_init(void)
 	if (board_is_evm_sk(&header))
 		config_ddr(303, &ioregs_evmsk, &ddr3_data,
 			   &ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0);
-	else if (board_is_bone_lt(&header))
+	else if (board_is_bone_lt(&header) || board_is_usomiq(&header))
 		config_ddr(400, &ioregs_bonelt,
 			   &ddr3_beagleblack_data,
 			   &ddr3_beagleblack_cmd_ctrl_data,
@@ -617,7 +588,7 @@ int board_eth_init(bd_t *bis)
 		puts("Could not get board ID.\n");
 
 	if (board_is_bone(&header) || board_is_bone_lt(&header) ||
-	    board_is_idk(&header)) {
+	    board_is_idk(&header) || board_is_usomiq(&header)) {
 		writel(MII_MODE_ENABLE, &cdev->miisel);
 		cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if =
 				PHY_INTERFACE_MODE_MII;
diff --git a/board/ti/am335x/board.h b/board/ti/am335x/board.h
index bc700d5..ea4bb67 100644
--- a/board/ti/am335x/board.h
+++ b/board/ti/am335x/board.h
@@ -60,6 +60,11 @@ static inline int board_is_evm_15_or_later(struct am335x_baseboard_id *header)
 		strncmp("1.5", header->version, 3) <= 0);
 }
 
+static inline int board_is_usomiq(struct am335x_baseboard_id *header)
+{
+	return !strncmp(header->name, "A335USOM", HDR_NAME_LEN);
+}
+
 /*
  * We have three pin mux functions that must exist.  We must be able to enable
  * uart0, for initial output and i2c0 to read the main EEPROM.  We then have a
diff --git a/board/ti/am335x/mux.c b/board/ti/am335x/mux.c
index f4bb9f8..2f6ce73 100644
--- a/board/ti/am335x/mux.c
+++ b/board/ti/am335x/mux.c
@@ -366,8 +366,18 @@ void enable_board_pin_mux(struct am335x_baseboard_id *header)
 #else
 		configure_module_pin_mux(mmc1_pin_mux);
 #endif
+    } else if (board_is_usomiq(header)) {
+        /* uSomIQ pinmux */
+        configure_module_pin_mux(i2c1_pin_mux);
+        configure_module_pin_mux(mii1_pin_mux);
+        configure_module_pin_mux(mmc0_pin_mux);
+        configure_module_pin_mux(nand_pin_mux);
 	} else {
-		puts("Unknown board, cannot configure pinmux.");
-		hang();
+        puts("Unknown board, configure pinmux for uSomIQ\n");
+        /* uSomIQ pinmux */
+        configure_module_pin_mux(i2c1_pin_mux);
+        configure_module_pin_mux(mii1_pin_mux);
+        configure_module_pin_mux(mmc0_pin_mux);
+        configure_module_pin_mux(nand_pin_mux);
 	}
 }
diff --git a/include/configs/am335x_evm.h b/include/configs/am335x_evm.h
index 476430d..9e9307b 100644
--- a/include/configs/am335x_evm.h
+++ b/include/configs/am335x_evm.h
@@ -62,8 +62,8 @@
 	"nandrootfstype=ubifs rootwait=1\0" \
 	"nandboot=echo Booting from nand ...; " \
 		"run nandargs; " \
-		"nand read ${fdtaddr} u-boot-spl-os; " \
-		"nand read ${loadaddr} kernel; " \
+		"nand read ${fdtaddr} NAND.u-boot-spl-os; " \
+		"nand read ${loadaddr} NAND.kernel; " \
 		"bootz ${loadaddr} - ${fdtaddr}\0"
 #else
 #define NANDARGS ""
@@ -174,6 +174,8 @@
 		"run ramargs; " \
 		"bootz ${loadaddr} ${rdaddr} ${fdtaddr}\0" \
 	"findfdt="\
+		"if test $board_name = A335USOM; then " \
+			"setenv fdtfile am335x-usomiq.dtb; fi; " \
 		"if test $board_name = A335BONE; then " \
 			"setenv fdtfile am335x-bone.dtb; fi; " \
 		"if test $board_name = A335BNLT; then " \
@@ -233,6 +235,72 @@
 
 #ifdef CONFIG_NAND
 /* NAND: device related configs */
+#ifdef CONFIG_NAND_4K
+#define CONFIG_SYS_NAND_PAGE_SIZE	4096
+#define CONFIG_SYS_NAND_OOBSIZE		224
+#define CONFIG_SYS_NAND_BLOCK_SIZE	(256*1024)
+#define CONFIG_SYS_NAND_PAGE_COUNT	(CONFIG_SYS_NAND_BLOCK_SIZE / \
+					 CONFIG_SYS_NAND_PAGE_SIZE)
+#define CONFIG_SYS_NAND_5_ADDR_CYCLE
+/* NAND: driver related configs */
+#define CONFIG_NAND_OMAP_GPMC
+#define CONFIG_NAND_OMAP_ELM
+#define CONFIG_SYS_NAND_ONFI_DETECTION
+#define CONFIG_NAND_OMAP_ECCSCHEME	OMAP_ECC_BCH16_CODE_HW
+#define CONFIG_SYS_NAND_BAD_BLOCK_POS	NAND_LARGE_BADBLOCK_POS
+#define CONFIG_SYS_NAND_ECCPOS	{ 2, 3, 4, 5, 6, 7, 8, 9, \
+				10, 11, 12, 13, 14, 15, 16, 17, 18, 19, \
+				20, 21, 22, 23, 24, 25, 26, 27, 28, 29, \
+				30, 31, 32, 33, 34, 35, 36, 37, 38, 39, \
+				40, 41, 42, 43, 44, 45, 46, 47, 48, 49, \
+				50, 51, 52, 53, 54, 55, 56, 57, 58, 59, \
+				60, 61, 62, 63, 64, 65, 66, 67, 68, 69, \
+				70, 71, 72, 73, 74, 75, 76, 77, 78, 79, \
+				80, 81, 82, 83, 84, 85, 86, 87, 88, 89, \
+				90, 91, 92, 93, 94, 95, 96, 97, 98, 99, \
+			100, 101, 102, 103, 104, 105, 106, 107, 108, 109, \
+			110, 111, 112, 113, 114, 115, 116, 117, 118, 119, \
+			120, 121, 122, 123, 124, 125, 126, 127, 128, 129, \
+			130, 131, 132, 133, 134, 135, 136, 137, 138, 139, \
+			140, 141, 142, 143, 144, 145, 146, 147, 148, 149, \
+			150, 151, 152, 153, 154, 155, 156, 157, 158, 159, \
+			160, 161, 162, 163, 164, 165, 166, 167, 168, 169, \
+			170, 171, 172, 173, 174, 175, 176, 177, 178, 179, \
+			180, 181, 182, 183, 184, 185, 186, 187, 188, 189, \
+			190, 191, 192, 193, 194, 195, 196, 197, 198, 199, \
+			200, 201, 202, 203, 204, 205, 206, 207, 208, 209, \
+			}
+#define CONFIG_SYS_NAND_ECCSIZE		512
+#define CONFIG_SYS_NAND_ECCBYTES	26
+#define MTDIDS_DEFAULT			"nand0=nand.0"
+#define MTDPARTS_DEFAULT		"mtdparts=nand.0:" \
+					"256k(NAND.SPL)," \
+					"256k(NAND.SPL.backup1)," \
+					"256k(NAND.SPL.backup2)," \
+					"256k(NAND.SPL.backup3)," \
+					"512k(NAND.u-boot-spl-os)," \
+					"1m(NAND.u-boot)," \
+					"256k(NAND.u-boot-env)," \
+					"256k(NAND.u-boot-env.backup1)," \
+					"7m(NAND.kernel)," \
+					"-(NAND.rootfs)"
+#define CONFIG_SYS_NAND_U_BOOT_OFFS	0x00180000
+#undef CONFIG_ENV_IS_NOWHERE
+#define CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_OFFSET		0x00280000
+#define CONFIG_ENV_OFFSET_REDUND	0x002c0000
+#define CONFIG_SYS_ENV_SECT_SIZE	CONFIG_SYS_NAND_BLOCK_SIZE
+/* NAND: SPL related configs */
+#ifdef CONFIG_SPL_NAND_SUPPORT
+#define CONFIG_SPL_NAND_AM33XX_BCH
+#endif
+/* NAND: SPL falcon mode configs */
+#ifdef CONFIG_SPL_OS_BOOT
+#define CONFIG_CMD_SPL_NAND_OFS		0x00100000 /* os parameters */
+#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS	0x00300000 /* kernel offset */
+#define CONFIG_CMD_SPL_WRITE_SIZE	CONFIG_SYS_NAND_BLOCK_SIZE
+#endif
+#else
 #define CONFIG_SYS_NAND_5_ADDR_CYCLE
 #define CONFIG_SYS_NAND_PAGE_COUNT	(CONFIG_SYS_NAND_BLOCK_SIZE / \
 					 CONFIG_SYS_NAND_PAGE_SIZE)
@@ -282,6 +350,7 @@
 #define CONFIG_SYS_NAND_SPL_KERNEL_OFFS	0x00200000 /* kernel offset */
 #define CONFIG_CMD_SPL_WRITE_SIZE	0x2000
 #endif
+#endif
 #endif /* !CONFIG_NAND */
 
 /*
